• DocumentCode
    880487
  • Title

    Reduction of RMS jitter and phase deviation in 10 Gbit/s timing recovery circuit using monolithic ICs

  • Author

    Ono, Takahito ; Hagimoto, Ken ; Nakamura, Mitsutoshi ; Ishihara, Noboru ; Kikuchi, Hiroaki

  • Author_Institution
    NTT Transmission Syst. Labs., Kanagawa, Japan
  • Volume
    28
  • Issue
    4
  • fYear
    1992
  • Firstpage
    403
  • Lastpage
    405
  • Abstract
    A 10 Gbit/s timing recovery circuit using GaAs IC technology is presented. A jitter suppression method using two cascaded differentiators is proposed. The phase deviation characteristics of a timing recovery circuit for mark density variation are also discussed.
  • Keywords
    III-V semiconductors; differentiating circuits; digital communication systems; digital integrated circuits; gallium arsenide; monolithic integrated circuits; optical communication equipment; stability; timing circuits; 10 Gbit/s; GaAs; IC technology; RMS jitter; cascaded differentiators; jitter suppression; mark density variation; monolithic ICs; phase deviation characteristics; timing recovery circuit;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19920253
  • Filename
    126392
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=880487