DocumentCode
880726
Title
A genetic algorithm for low variance control in semiconductor device manufacturing: some early results
Author
Rietman, Edward A. ; Frye, Robert C.
Author_Institution
Lucent Technols., bell Labs., Murray Hill, NJ, USA
Volume
9
Issue
2
fYear
1996
fDate
5/1/1996 12:00:00 AM
Firstpage
223
Lastpage
229
Abstract
Genetic algorithms are a computational paradigm modeled after biological genetics. They allow one to efficiently search a very large optimization space for good solutions. In this paper we describe the use of a genetic algorithm for developing robust plasma etch recipes that reduce the variance about a target mean and allow the dc bias to drift within 15% of a nominal value. The tapered via etch process in our production facility results in a oxide films of about 7093 Å and a standard deviation of 730 Å. In simulations using real production data and a neural network model of the process our new recipes have reduced the standard deviation below 200 Å. These results indicate that significant improvement in the process can be realized by applying these techniques
Keywords
CMOS integrated circuits; genetic algorithms; integrated circuit manufacture; neural nets; optimal control; process control; sputter etching; 7093 angstrom; CMOS integrated circuits; computational paradigm; dc bias; genetic algorithm; neural network model; optimization space; process variance; production facility; robust plasma etch recipes; semiconductor device manufacturing; standard deviation; tapered via etch process; Biological system modeling; Biology computing; Computational modeling; Etching; Genetic algorithms; Neural networks; Plasma applications; Plasma simulation; Production facilities; Robustness;
fLanguage
English
Journal_Title
Semiconductor Manufacturing, IEEE Transactions on
Publisher
ieee
ISSN
0894-6507
Type
jour
DOI
10.1109/66.492816
Filename
492816
Link To Document