Modeling of integrated circuit yield loss mechanisms

Author

Stamenkovic, Z. ; Stojadinovic, N. ; Dimitrijev, S.

Author_Institution

Fac. of Electron. Eng., Nis Univ., Serbia

Volume

9

Issue

2

fYear

1996

fDate

5/1/1996 12:00:00 AM

Firstpage

270

Lastpage

272

Abstract

A yield model suited for application in a yield control system and based on in-line inspections of control wafers containing the corresponding test structures has been proposed. It is shown that the proposed yield model and yield control system can be used for modeling yield loss mechanisms and predicting efficient investments which are required in order to ensure a competitive yield of integrated circuits. An approach for the extraction of chip critical areas associated with the corresponding yield loss mechanism has been described

Keywords

inspection; integrated circuit measurement; integrated circuit modelling; integrated circuit yield; IC test structures; IC yield model; chip critical areas extraction; control wafers; in-line inspection; integrated circuit yield; investment; yield control system; yield loss mechanisms; Circuit faults; Circuit testing; Control system synthesis; Inspection; Integrated circuit modeling; Integrated circuit testing; Integrated circuit yield; Investments; Predictive models; Semiconductor device modeling;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.492821

Filename

492821