Title :
Wafer level sort programming-impact on EPROM memory retention
Author :
Yeoh, Teong-San ; Hu, Shze-Jer
Author_Institution :
Universiti Sains Malaysia, Malaysia
fDate :
5/1/1996 12:00:00 AM
Abstract :
Programming of EPROM microcontrollers normally takes place at the backend test operations. However, programming is best done at the wafer level sort testing operation as it is cost effective and entails the least handling. However, there are certain risks with the latter. EPROM memory retention is a quality and reliability concern if there is any EPROM memory charge loss due to heat treatments induced during assembly processing. This paper deals with the theories and evaluations to support programming at the wafer sort operation
Keywords :
EPROM; PLD programming; integrated circuit manufacture; integrated circuit reliability; microcontrollers; EPROM memory retention; EPROM microcontrollers; memory charge loss; reliability; wafer level sort programming; wafer level sort testing operation; Assembly; Costs; Dielectric substrates; EPROM; Manufacturing; Microcontrollers; Nonvolatile memory; Physics; Read only memory; Testing;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
