Title :
A monolithic 8-bit D/A converter with a new scheme for error compensation
Author :
Shoji, Mamoru ; Saari, V.R.
Abstract :
Discusses a modification of a monolithic bipolar 8-bit D/A converter (DAC) circuit based on the R-2R ladder method. It does not require transistor emitter size scaling. Voltages proportional to absolute temperature are introduced between the bases of the current generator transistors to compensate for the differences in their emitter-base voltages and thus maintain precision in the current division of the R-2R ladder. The compensation obtained by this method is adequate for 9- and 10-bit monolithic DAC´s operating in a temperature range from -40/spl deg/C to 125/spl deg/C.
Keywords :
Bipolar transistors; Convertors; Digital-analogue conversion; Error compensation; Monolithic integrated circuits; bipolar transistors; convertors; digital-analogue conversion; error compensation; monolithic integrated circuits; Channel bank filters; Circuits; Computational modeling; Computer simulation; Error compensation; Parasitic capacitance; Signal to noise ratio; Switches; Telephony; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1975.1050647
