• DocumentCode
    881303
  • Title

    Charge Collection in CMOS/SOS Structures

  • Author

    Campbell, A.B. ; Knudson, A.R. ; Stapor, W.J. ; Shapiro, P. ; Diehl-Nagle, S.E. ; Hauser, J.

  • Author_Institution
    Naval Research Laboratory Washington, D.C. 20375-5000
  • Volume
    32
  • Issue
    6
  • fYear
    1985
  • Firstpage
    4128
  • Lastpage
    4132
  • Abstract
    Charge collection measurements in CMOS/SOS test structures have shown that even for highly ionizing ion tracks the fraction of the charge collected at a node is about equal to what is expected from the amount deposited in the silicon layer and that no charge is collected from the sapphire substrate.
  • Keywords
    CMOS integrated circuits; CMOS technology; Charge measurement; Current measurement; FETs; Insulation life; Silicon; Single event upset; Substrates; Testing;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.1985.4334080
  • Filename
    4334080
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=881303