Comparison of 2D Memory SEU Transport Simulation with Experiments

Single event upset (SEU) simulations in SRAM cells have been carried out and the results are compared to experimental data on 16K bit memories. The simulations consisted of simultaneous calculations of charge transport and transient circuit response for four cross-coupled CMOS transistors following the introduction of a slab of excess carriers into the "off" p-channel drain. The experiments collected upset rates produced in the memories by 163 MeV argon ions directed normally to the chip surface. Agreement between experiment and calculation was achieved when (1) the p-channel transistors were integrated into a single block of silicon as in the memory cell layout and (2) scaling was done on the Auger coefficients to compensate for an inherent 2D effect.