Scaling of surface-channel charge-coupled devices

Improvement in lithographic resolution will enable designers to reduce the area of charge-coupled device (CCD) memories. However, if only lateral dimensions are scaled down, the transfer inefficiency will increase. The transfer inefficiency is determined primarily by surface states or by barrier-modulation effects. A scaling procedure is described which will allow transfer inefficiency to be unchanged as the cell size is reduced by scaling other CCD parameters such that the normalized potential distribution under the gates is maintained. The normalized potential distribution can be maintained in two ways: 1) constant gate voltage scaling, which has the advantage of better S/N (because higher charges are handled) but is limited by electrical breakdown and 2) constant field scaling which avoids this limit but has a poorer S/N. A sample calculation shows that signal deterioration at smaller cell sizes is still dominated by the transfer-inefficiency effects rather than the noise effects.