• DocumentCode
    881785
  • Title

    Improvement of the majority gate algorithm for grey scale dilation/erosion

  • Author

    Gasteratos, A. ; Andreadis, I. ; Tsalides, P.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece
  • Volume
    32
  • Issue
    9
  • fYear
    1996
  • fDate
    4/25/1996 12:00:00 AM
  • Firstpage
    806
  • Lastpage
    807
  • Abstract
    An improvement of the majority gate algorithm suitable for grey scale morphological operations is presented in the Letter. The redundancy of temporal signals led to a simplified hardware implementation. It is shown that max/min operators can be computed by the same circuit. A new pipelined systolic array architecture based on this circuit is illustrated for dilation/erosion operations
  • Keywords
    filtering theory; image processing; mathematical morphology; systolic arrays; filtering algorithm; grey scale dilation/erosion; hardware implementation; image processing; majority gate algorithm; max/min operators; morphological operations; pipelined systolic array architecture; temporal signal redundancy;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19960529
  • Filename
    492933
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=881785