DocumentCode
882075
Title
Reduced implementation of D-type DET flip-flops
Author
Gago, A. ; Escaño, R. ; Hidalgo, J.A.
Author_Institution
Departamento de Arquitecture y Tecnologia de Computadores y Electronica, Malaga Univ., Spain
Volume
28
Issue
3
fYear
1993
fDate
3/1/1993 12:00:00 AM
Firstpage
400
Lastpage
402
Abstract
One of the main disadvantages of using D-type double-edge triggered flip-flops (DET-FFs) in VLSI system design is the number of transistors required. Two new DET-FF circuits (one static, the other dynamic) are proposed in which the number of transistors is reduced to a number similar to that for classic single-edge triggered flip-flops (SET-FFs). Both new circuits not only behave correctly when operated at high frequency but also offer a good level of immunity to metastability problems (static) and race problems (dynamic), as well as presenting a simple straightforward layout. These considerations offer wider practical and economic applications for the use of DET-FFs in VLSI system design
Keywords
CMOS integrated circuits; VLSI; flip-flops; integrated logic circuits; D-type; VLSI system design; double-edge triggered; flip-flops; high frequency; Circuits; Clocks; Energy consumption; Flip-flops; Frequency; Inverters; MOSFETs; Metastasis; Switches; Very large scale integration;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.210012
Filename
210012
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