• DocumentCode
    882135
  • Title

    The Production of Completion Signals by Asynchronous, Iterative Networks

  • Author

    Waite, William M.

  • Author_Institution
    Department of Electrical Engineering, Columbia University, New York, N. Y.
  • Issue
    2
  • fYear
    1964
  • fDate
    4/1/1964 12:00:00 AM
  • Firstpage
    83
  • Lastpage
    86
  • Abstract
    In a synchronous circuit an operation is complete when a given number of clock times have elapsed since it was begun. In an asynchronous network no such indication is available, and we must either rely on the network to inform us of completion, or wait for the worst-case delay. The second method is undesirable because normally the network will complete its operation long before the worst-case delay time has elasped. It will be shown here that, for a large class of iterative circuits, the network can be designed to inform us of completion. Moreover, this can be done without recourse to monitoring all lateral states (to see when none are changing).
  • Keywords
    Adders; Circuits; Clocks; Delay effects; Iterative methods; Logic arrays; Monitoring; Production; Propagation delay; Wires;
  • fLanguage
    English
  • Journal_Title
    Electronic Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0367-7508
  • Type

    jour

  • DOI
    10.1109/PGEC.1964.263775
  • Filename
    4038103