A 6-ns 1-Mb CMOS SRAM with latched sense amplifier

Author

Seki, Teruo ; Itoh, Eisaku ; Furukawa, Chiaki ; Maeno, Isamu ; Ozawa, Tadashi ; Sano, Hiroyuki ; Suzuki, Noriyuki

Author_Institution

Fujitsu VLSI Ltd., Aichi, Japan

Volume

28

Issue

4

fYear

1993

fDate

4/1/1993 12:00:00 AM

Firstpage

478

Lastpage

483

Abstract

A 1-Mb (256 K×4) CMOS SRAM with 6-ns access time is described. The SRAM, having a cell size of 3.8 μm×7.2 μm and a die size of 6.09 mm×12.94 mm, is fabricated by using 0.5-μm triple-polysilicon and double-metal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new NMOS source-controlled latched sense amplifier and a data-output prereset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle

Keywords

CMOS integrated circuits; SRAM chips; 0.5 micron; 1 Mbit; 100 MHz; 52 mA; 6 ns; CMOS SRAM; NMOS source-controlled; Si; access time; data-output prereset circuit; double-metal process technology; equalizing technique; latched sense amplifier; power dissipation; static RAM; triple-polysilicon; CMOS technology; Decoding; Delay effects; Driver circuits; Inverters; MOS devices; Power dissipation; Pulse amplifiers; Random access memory; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.210031

Filename

210031