Design techniques for high-throughput BiCMOS self-timed SRAMs

Author

Yokomizo, Koichi ; Naito, Kuniyoshi

Author_Institution

Oki Electric Ind. Co. Ltd., Tokyo, Japan

Volume

28

Issue

4

fYear

1993

fDate

4/1/1993 12:00:00 AM

Firstpage

484

Lastpage

489

Abstract

Design techniques for a high-throughput BiCMOS self-timed SRAM are described. A new BiCMOS read circuit using a pipelined read architecture and a BiCMOS complementary clocked driver (BCCD) are proposed to reduce the operating cycle time. A 8192×9-b dual-port self-timed SRAM designed using the proposed techniques achieved a clock cycle time of 3.0 ns, that is, a 333-MHz operating frequency, by SPICE simulation on model parameters for 0.8-μm BiCMOS technology. A high-speed built-in self-test (BIST) circuit was studied and designed for the 3.0-ns cycle SRAM. It is confirmed that the BIST circuit allows the 3.0-ns cycle SRAM to test at its maximum operating frequency

Keywords

BiCMOS integrated circuits; SPICE; SRAM chips; built-in self test; integrated circuit testing; 0.8 micron; 3 ns; 333 MHz; BIST circuit; BiCMOS; SPICE simulation; built-in self-test; complementary clocked driver; dual port static RAM; high-speed; high-throughput; model parameters; pipelined read architecture; self-timed SRAM; Asynchronous transfer mode; BiCMOS integrated circuits; Built-in self-test; Circuit testing; Clocks; Driver circuits; Frequency; Random access memory; Switches; Throughput;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.210032

Filename

210032