A 500-megabyte/s data-rate 4.5 M DRAM

Author

Kushiyama, Natsuki ; Ohshima, Shigeo ; Stark, Don ; Noji, Hiroyuki ; Sakurai, Kiyofumi ; Takase, Satoru ; Furuyama, Tohru ; Barth, Richard M. ; Chan, Andy ; Dillon, John ; Gasbarro, James A. ; Griffin, Matthew M. ; Horowitz, Mark ; Lee, Thomas H. ; Lee, V

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

28

Issue

4

fYear

1993

fDate

4/1/1993 12:00:00 AM

Firstpage

490

Lastpage

498

Abstract

A 512-kb×9 DRAM with a 500-Mbyte/s data transfer rate was developed. This high data rate was achieved by designing a DRAM core with a very high internal column bandwidth, and coupling this core with a block-oriented, small-swing, synchronous interface that uses skew-canceling clocks. The DRAM has a 1-kbyte×2-line sense-amp cache and is assembled in a 32-pin vertical surface-mount-type plastic package. The measurement results clearly verified the 500-Mbyte/s data rate

Keywords

CMOS integrated circuits; DRAM chips; surface mount technology; 4.5 Mbit; 4608 kbit; 500 Mbyte/s; CMOS process; DRAM; data transfer rate; dynamic RAM; plastic package; sense-amp cache; skew-canceling clocks; surface-mount-type; synchronous interface; vertical SMD package; Access protocols; Bandwidth; Central Processing Unit; Graphics; Packaging; Pins; Random access memory; Resistors; System buses; Wires;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.210033

Filename

210033