A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture

Author

Kobayashi, Tsuguo ; Nogami, Kazutaka ; Shirotori, Tsukasa ; Fujimoto, Yukihiro

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

28

Issue

4

fYear

1993

fDate

4/1/1993 12:00:00 AM

Firstpage

523

Lastpage

527

Abstract

Two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described. One is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically. This sense amplifier reduces power without degrading access time compared with the conventional current-mirror sense amplifier. The other is a static power-saving input buffer (SPSIB) that reduces DC current in interface circuits receiving TTL high input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM

Keywords

SRAM chips; VLSI; amplifiers; buffer circuits; 512 kbit; TTL high input level; current-controlled; high-speed SRAM; interface circuits; large-scale memory; latch sense amplifier; low-power architecture; static RAM; static power-saving input buffer; Bandwidth; Batteries; Instruction sets; Large-scale systems; Latches; MOSFET circuits; Operational amplifiers; Power amplifiers; Power dissipation; Random access memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.210039

Filename

210039