Digital system design in the presence of single event upsets

Author

Karp, Sherman ; Gilbert, Barry K.

Author_Institution

Mayo Found., Rochester, MN, USA

Volume

29

Issue

2

fYear

1993

fDate

4/1/1993 12:00:00 AM

Firstpage

310

Lastpage

316

Abstract

The authors consider the effects of single event upsets (SEUs) on digital systems, and show techniques for designing reliable systems with current levels of SEU protection. Three main systems are discussed: main memory, logic, and cache memory. A design for the main and cache memory subsystems that are SEU protected is also described. With SEU defined in bit days p, and using single error correction, it is shown that for all subsystems considered, an effective upset rate which is proportional to the product of p² and the time between corrections, or scrub time, can be obtained. Data for memory chip size and performance derived from the gallium-arsenide (GaAs) pilot lines funded by the Defense Advanced Research Projects Agency (DARPA) throughout the 1980s are used

Keywords

III-V semiconductors; VLSI; buffer storage; error correction; fault tolerant computing; gallium arsenide; integrated logic circuits; integrated memory circuits; logic design; protection; DARPA; Defense Advanced Research Projects Agency; GaAs; VLSI; bit days; cache memory; digital systems; effective upset rate; logic design; main memory; memory chip size; performance; pilot lines; protection; scrub time; single error correction; single event upsets; Cache memory; Digital systems; Error correction codes; Gallium arsenide; Large scale integration; Logic circuits; Protection; Random access memory; Single event upset; Very large scale integration;

fLanguage

English

Journal_Title

Aerospace and Electronic Systems, IEEE Transactions on

Publisher

ieee

ISSN

0018-9251

Type

jour

DOI

10.1109/7.210069

Filename

210069