• DocumentCode
    883099
  • Title

    Performance implications of tolerating cache faults

  • Author

    Pour, Andreas Farid ; Hill, Mark D.

  • Author_Institution
    Michigan Univ. Law School, Ann Arbor, MI, USA
  • Volume
    42
  • Issue
    3
  • fYear
    1993
  • fDate
    3/1/1993 12:00:00 AM
  • Firstpage
    257
  • Lastpage
    267
  • Abstract
    The authors investigate how much cache miss ratios increase when blocks are disabled. It is shown how the mean miss ratio increase can be characterized as a function of the miss ratios of related caches, an efficient approach is developed for calculating the exact distribution of miss ratio increases from all fault patterns, and this approach is applied to the ATUM traces (see A. Agarwal et al., 1986). Results reveal that the mean relative miss ratio increase from a few faults decreases with increasing cache size and is negligible (<2% per defect) unless a set is completely disabled by faults. The maximum relative increase is also acceptable (5% per fault) if no set is entirely disabled
  • Keywords
    buffer storage; fault tolerant computing; performance evaluation; ATUM traces; cache faults; fault patterns; performance implications; Circuit faults; Computer architecture; Computer errors; Costs; Delay; Error correction codes; Fault tolerance; Manufacturing; Microprocessors; Writing;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.210168
  • Filename
    210168