Schottky I/sup 2/L (substrate fed logic) - An analysis of the implications of the vertical injector structure and Schottky collection

The DC behavior of a Schottky I/SUP 2/L gate is analysed by using the Ebers-Moll equations, modified to include Schottky diodes. The usual definition of I/SUP 2/L common emitter current gain is replaced by a new definition which is more suitable for the vertical injector structure of Schottky I/SUP 2/L. The analysis is general and can be applied to any multijunction structure containing Schottky diodes or having a distributed current source. This framework is used to examine the effect on the fan-out of minority carrier collection at the Schottky contacts. Equations are presented which relate both the recombination at the Schottky contacts and the vertical reinjection through the inverse p-n-p transistor to the device structure.