Title :
Modeling device and layout effects of performance driven I/sup 2/L
Author :
Gaffney, Donald P. ; Bhattacharyya, A.
fDate :
4/1/1977 12:00:00 AM
Abstract :
The performance of I/SUP 2/L gates at high injector current levels has been shown to be dependent on minority carrier charge storage and fan-out. These models, however, do not include the effects of extrinsic base resistance, parasitic diode shunting, and lateral p-n-p high level injection on the speed-power product curve. This paper considers these three factors with the aid of a device model, circuit simulations, and test data from logic race structures.
Keywords :
Bipolar integrated circuits; Integrated logic circuits; Semiconductor device models; bipolar integrated circuits; integrated logic circuits; semiconductor device models; Circuit simulation; Circuit testing; Delay effects; Diodes; Doping; Inverters; Logic testing; Metallization; Propagation delay; Upper bound;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1977.1050865
