DocumentCode
883644
Title
Schottky collector I/sup 2/L
Author
Blackstone, S.C. ; Mertens, R.P.
Volume
12
Issue
3
fYear
1977
fDate
6/1/1977 12:00:00 AM
Firstpage
270
Lastpage
275
Abstract
A new I/SUP 2/L gate which promises increased packing density and increased speed is discussed. It incorporates the use of a Schottky contact as the collector of the vertical switching transistor of an I/SUP 2/L gate. Calculations and experiments show that the problems associated with this structure (low downward beta) can be controlled by limiting both the fan-out and the fan-in. Delays of less than 10 ns have been measured using a 10-/spl mu/m technology and a 6-/spl mu/m-thick epi. A divide-by-two circuit with a maximum toggle frequency of 12.5 MHz has been built. The additional fan-in limitation of the logic is described.
Keywords
Bipolar integrated circuits; Integrated logic circuits; bipolar integrated circuits; integrated logic circuits; Controllability; Delay; Electron devices; P-n junctions; Process design; Schottky barriers; Silicon; Solid state circuits; Springs; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1977.1050890
Filename
1050890
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