A serial-parallel multiplier using the NENDEP technology

A 12-bit serial-parallel multiplier has been integrated in the NENDEP technology. The features of a logic circuit using dynamic two-phase ratioed logic, combined with depletion load devices, are described. The basic cell structure of the multiplier, which accepts both positive and negative numbers represented in the two´s complement code, is given. Next the performance of the 12-bit multiplier is reported. The circuit operates at a frequency of 5 MHz with a 5-V supply and 0- to 12-V clock signals. Inputs and output are directly TTL-compatible. At higher voltages clock rates up to 7 MHz are allowed.