DocumentCode
883817
Title
Depletion-isolation effect in vertical MOSFETs during the transition from partial to fully depleted operation
Author
Hakim, M.M.A. ; de Groot, C.H. ; Gili, E. ; Uchino, T. ; Hall, S. ; Ashburn, P.
Author_Institution
Microelectron. Group, Univ. of Southampton, UK
Volume
53
Issue
4
fYear
2006
fDate
4/1/2006 12:00:00 AM
Firstpage
929
Lastpage
932
Abstract
A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10nm. For pillar thicknesses between 200-60nm, the output characteristics with and without impact ionization are identical at a low drain bias and then diverge at a high drain bias. The critical drain bias Vdc for which the increased drain-current is observed is found to decrease with a reduction in pillar thickness. This is explained by the onset of FBEs at progressively lower values of the drain bias due to the merging of the drain depletion regions at the bottom of the pillar (depletion isolation). For pillar thicknesses between 60-10nm, the output characteristics show the opposite behavior, namely, the critical drain bias increases with a reduction in pillar thickness. This is explained by a reduction in the severity of the FBEs due to the drain debiasing effect caused by the elevated body potential. Both depletion isolation and gate-gate coupling contribute to the drain-current for pillar thicknesses between 100-40nm.
Keywords
MOSFET; circuit simulation; isolation technology; 10 to 200 nm; depletion isolation effect; drain-current; floating body effect; pillar thickness; vertical MOSFET; CMOS technology; FETs; FinFETs; Impact ionization; Isolation technology; Low voltage; MOSFETs; Merging; Silicon on insulator technology; Threshold voltage; Depletion isolation; fully depleted (FD); partially depleted (PD); vertical MOSFETs (VMOS);
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2006.871182
Filename
1610933
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