Title :
CMOS analogue current-steering multiplier
Author_Institution :
Dept. of Electr. & Electron. Eng., Pretoria Univ., South Africa
fDate :
3/12/1992 12:00:00 AM
Abstract :
A four-quadrant multiplier circuit for realisation in CMOS is proposed and compromises between characteristics of the design are discussed. The design is optimised for use in the analogue VLSI implementation of neutral networks and the results presented demonstrate that the circuit complies with the requirements of this application.
Keywords :
CMOS integrated circuits; VLSI; linear integrated circuits; multiplying circuits; neural nets; CMOS analogue current-steering multiplier; analogue VLSI; four-quadrant multiplier circuit; neutral networks;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19920331
