Title :
A standardized approach for the reduction of LSI design time and automatic rules checking
Author :
Bertails, Jean-Claude ; Zirphile, Jean
Abstract :
A design method, based upon the use of standardized basic elements is proposed. A symbolic layout technique, associated with network recognition programs, enables a fast and secure design. That method has been applied to CMOS technology and practical results demonstrate its efficiency.
Keywords :
Circuit layout CAD; Field effect integrated circuits; Large scale integration; circuit layout CAD; field effect integrated circuits; large scale integration; CMOS technology; Circuit simulation; Circuit synthesis; Computer graphics; Design automation; Design methodology; Design optimization; Large scale integration; Layout; Routing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1977.1050929
