DocumentCode
884209
Title
Two static 4K clocked and nonclocked RAM designs
Author
Connell, Timothy R O ; Hartman, John M. ; Errett, B. ; Leach, George S.
Volume
12
Issue
5
fYear
1977
fDate
10/1/1977 12:00:00 AM
Firstpage
497
Lastpage
501
Abstract
A detailed description of both a clocked and a nonclocked n-channel MOS 4K static RAM is presented. The clocked device is a three-supply (+12 V, +5 V, -5 V) RAM which uses bootstrapping circuitry for signal driving, and sustaining resistors for low memory array power dissipation and infinite chip select length. The nonclocked device is a single supply (+5 V) fully TTL compatible RAM with depletion load circuitry for speed and compactness. Emphasis is given to processing parameters and performances as well as circuit design considerations including internal signal timings and circuit schematics.
Keywords
Field effect integrated circuits; Integrated memory circuits; Random-access storage; field effect integrated circuits; integrated memory circuits; random-access storage; Circuit synthesis; Clocks; Conductivity; Ion implantation; Microprocessors; Power dissipation; Random access memory; Read-write memory; Resistors; Timing;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1977.1050942
Filename
1050942
Link To Document