Title :
Analysis and Design of RF CMOS Attenuators
Author :
Dogan, Hakan ; Meyer, Robert G. ; Niknejad, Ali M.
Author_Institution :
Atheros Commun., Santa Clara, CA
Abstract :
Attenuators are analyzed for their minimum Insertion Loss (IL), maximum attenuation and source-load matching performance. These results are used to make trade-offs in the design of a CMOS attenuator with wide dynamic range, designed and fabricated in a 0.13 mum CMOS process. The design employs two non-identical cascaded T-stages that are activated consecutively to improve linearity. The design operates in the frequency band of DC-2.5 GHz with 0.9-3.5 dB insertion loss and 42 dB maximum attenuation in the entire frequency range. Worst case S11 is - 8.2 dB across the frequency band. The design achieves an IIP3 of + 20 dBm at mid-attenuation.
Keywords :
CMOS analogue integrated circuits; UHF integrated circuits; attenuators; impedance matching; integrated circuit design; CMOS process; RF CMOS attenuators design; frequency 2.5 GHz; impedance matching; loss 0.9 dB to 3.5 dB; maximum attenuation performance; minimum insertion loss analysis; nonidentical cascaded T-stages; size 0.13 mum; source-load matching performance; Attenuation; Attenuators; CMOS process; Dynamic range; Insertion loss; Linearity; Performance analysis; Performance loss; Process design; Radio frequency; Attenuator; CMOS attenuator; RF attenuator; attenuation control loop; attenuator analysis; highly linear attenuator; parasitic effects on attenuators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2008.2004325
