An integrated reset/pulse pile-up rejection circuit for pixel readout ASICs

Author

Bastia, P. ; Bertuccio, G. ; Borghetti, F. ; Caccia, S. ; Ferragina, V. ; Ferrari, F. ; Maiocchi, D. ; Malcovati, P. ; Martin, D. ; Pullia, A. ; Ratti, N.

Author_Institution

Padana Superiore, Vimodrone

Volume

53

Issue

1

fYear

2006

Firstpage

414

Lastpage

417

Abstract

We present a compact and low power integrated circuit designed to control the reset and perform pulse pile-up rejection in multi-channel spectroscopic-grade ASICs. The circuit has been implemented in a 0.35 mum CMOS technology using an area of 60times80 mum² and null static power consumption. These features make this circuit suitable to be embedded into the front-end readout cells for spectroscopy/imaging X- and gamma-ray pixel detectors

Keywords

CMOS integrated circuits; X-ray spectroscopy; application specific integrated circuits; gamma-ray spectroscopy; nuclear electronics; position sensitive particle detectors; readout electronics; 0.35 mum; 60 mum; 80 mum; X-ray pixel detectors; X-ray spectroscopy; front-end readout cells; gamma-ray pixel detectors; gamma-ray spectroscopy; integrated reset-pulse pile-up rejection circuit; multichannel spectroscopic-grade ASIC; null static power consumption; pixel readout ASIC; CMOS technology; Energy consumption; Gamma ray detection; Gamma ray detectors; Integrated circuit technology; Optical imaging; Pixel; Power integrated circuits; Pulse circuits; Spectroscopy; Application specific integrated circuit; X-ray detector; front end electronics; pixel detector; semiconductor detector;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2006.869852

Filename

1611013