DC transfer characteristic, offset voltage sensitivities, and CMRR of FET differential stages

Using a simple square-law model of the field-effect transistor, the nonlinear dc transfer characteristic of FET differential stages is described for matched and unmatched input transistors. The input offset voltage sensitivities with respect to small imbalances of FET parameters and load device values are calculated for different load configurations. The common-mode rejection ratio (CMRR) is also considered.