Antiparallel Control Logic

This paper proposes a method, termed antiparallel control logic, for the control and efficient utilization of computer networks that exhibit substantial propagation delays on the lines interconnecting the logical elements, as well as in the elements themselves. The discussion encompasses the basic behavior of antiparallel stages that realize this method of control, including their logical realization and their extension to other useful network logic structures. In a strictly feedforward line, where the stored data are indexed forward by control pulses moving in a direction away from the data source, the existence of time variations in the delays of successive stages implies a nonzero probability that two successive control pulses will eventually appear at the inputs to a given stage so closely spaced that the basic reaction time of the stage is violated. The result is a failure of the transfer mechanism and a consequent loss of information. If feedback control is provided such that control pulses move in a direction opposite to the flow of information, that is, if the control and information flows are antiparallel, then the failure of the transfer mechanism does not cause an overlap in the information stored on the line, but rather leaves a void, or hole, which does not imply necessary information loss nor physically unrealizable storage requirements on the individual stages.