Substrate voltage bounce in NMOS self-biased substrates

The problem of substrate voltage bounce is discussed for NMOS LSI random logic designs which operate from self-biased substrates. Using chip capacitance and switching noise probability models, the impact of voltage bounce on threshold voltage variation (V/SUB T/-sigma) is illustrated and a comparison is made with designs operating from externally biased substrates. To achieve the potential performance improvement made possible through the use of substrate generators, off-chip capacitors are recommended to improve V/SUB T/-sigma control.