High-speed NMOS circuits for ROM-accumulator and multiplier type digital filters

Using a standard 6 μm NMOS silicon-gate process, circuit techniques are described for the full integration of high-speed ROM-accumulator and multiplier type digital filters. The ROM-accumulator structure is integrated using a new two-clock four-phase technique which can be used both for ROM and accumulator. An operating speed of 20 Mbits/s is measured. The circuit shows that an eighth-order filter on a 20 mm/SUP 2/ chip, dissipating only 400 mW at 10 Mbits/s is feasible. Using a 4-clock 4-phase technique a 4-bit serial-parallel multiplier is presented featuring 20 Mbits/s operation into a 15 pF load. Power dissipation is 7 mW/cell. Cell area is 0.2 mm/SUP 2/.