DocumentCode
885977
Title
A 64Kx1 bit dynamic ED-MOS RAM
Author
Wada, Toshio ; Kudoh, Osamu ; Sakamoto, Mitsuru ; Yamanaka, Hiroshi ; Nakamura, Kunio ; Kamoshida, Mototaka
Volume
13
Issue
5
fYear
1978
Firstpage
600
Lastpage
606
Abstract
A 64K/spl times/1 bit dynamic RAM based on an innovative short channel ED-MOS process technology and an improved ED-MOS sense amplifier circuit has been realized. The RAM has been designed by using 2-3 /spl mu/m design rules and employing ED-MOS peripheral circuits capable of low supply voltage operation. As a result, dynamic memory operation has been demonstrated with an access time less than 140 ns and a cycle time of 350 ns, using a single 5 V power supply.
Keywords
Field effect integrated circuits; Integrated circuit technology; Integrated memory circuits; Large scale integration; Random-access storage; field effect integrated circuits; integrated circuit technology; integrated memory circuits; large scale integration; random-access storage; Boron; Circuits; DRAM chips; Oxidation; Power supplies; Production; Random access memory; Read-write memory; Silicon; Substrates;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1978.1051106
Filename
1051106
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