DocumentCode
885987
Title
A 150 ns, 150 mW, 64K dynamic MOS RAM
Author
Wada, Toshio ; Takada, Masahide ; Matsue, Shigeki ; Kamoshida, Mototaka ; Suzuki, Shun-Ichi
Volume
13
Issue
5
fYear
1978
Firstpage
607
Lastpage
611
Abstract
A 64K dynamic MOS RAM organized as 16K words/spl times/4 bits has been realized by short-channel and single-level polysilicon gate technologies. The RAM uses 2 /spl mu/m effective channel length (L/SUB eff/), and 400 /spl Aring/ gate oxide film thickness (t/SUB ox/) transistors as active elements. Also, the RAM with a newly designed sense amplifier has successfully been fabricated using only four photo resist masking processes. The access time and power dissipation are 150 ns and 150 mW, respectively, at the cycle time of 400 ns.
Keywords
Field effect integrated circuits; Integrated circuit technology; Integrated memory circuits; Large scale integration; Random-access storage; field effect integrated circuits; integrated circuit technology; integrated memory circuits; large scale integration; random-access storage; Flip-flops; Large-scale systems; Length measurement; MOSFETs; Manufacturing; Power amplifiers; Power dissipation; Production; Read-write memory; Threshold voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1978.1051107
Filename
1051107
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