Dual-Bit Gate-Sidewall Storage FinFET NVM and New Method of Charge Detection

Author

Padilla, Alvaro ; Shin, Kyoungsub ; Tsu-Jae King Liu ; Hyun, Jae Woong ; Yoo, Inkyeong ; Park, Yoondong

Author_Institution

Univ. of California, Berkeley

Volume

28

Issue

6

fYear

2007

fDate

6/1/2007 12:00:00 AM

Firstpage

502

Lastpage

505

Abstract

A FinFET-based nonvolatile memory (NVM) cell design with two separate gate-sidewall charge-storage sites is presented for the first time. The conventional read method and/or a newly proposed read method can be used to identify the charge- storage state of each bit in the cell. The new read method allows the state of each bit to be determined by a forward read operation, and it is compatible with a gate-overlapped source/drain structure that offers improved ON-state conductance in contrast to the conventional read method. The dual-bit FinFET cell design can be used to achieve very high NVM storage density because of its high scalability and compatibility with standard CMOS process technology.

Keywords

MOSFET; logic design; random-access storage; semiconductor device models; CMOS process technology; FinFET NVM; ON-state conductance; charge detection; dual-bit gate-sidewall storage; nonvolatile memory cell design; read method; Electrodes; FETs; FinFETs; Flash memory; Interference; MOSFETs; Nonvolatile memory; SONOS devices; Scalability; Silicon on insulator technology; Band-to-band electron injection; FinFET; field-effect transistor (FET); gate-induced drain leakage (GIDL); nonvolatile memory (NVM);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2007.896786

Filename

4212187