DocumentCode
886029
Title
A 50 ns 4K static DSA MOS RAM
Author
Shimotori, Kazuhiro ; Ohmori, Masashi ; Ohkura, Isao ; Nakano, Takao ; Nagayama, Yasuji
Volume
13
Issue
5
fYear
1978
Firstpage
639
Lastpage
646
Abstract
An advanced DSA MOS (DMOS) technology is discussed as it applies to a high-speed 4K bit semiconductor static memory. It uses a polysilicon gate length of 4 /spl mu/m, a gate oxide thickness less than 800 /spl Aring/, and a shallow junction depth (<0.6 /spl mu/m) using conventional photolithographic methods. With these features, the effective channel length of the DSA MOST was reduced to 0.5 /spl mu/m and a smaller junction capacitance was obtained by the use of a high-resistivity (100-200 /spl Omega/.cm) substrate without a substrate bias generator. Combined with the depletion load transistors and selective oxidation processing, a static RAM of 50 ns access time at 630 mW power dissipation, die size of 5.24/spl times/5.36 mm/SUP 2/, and cell size of 53/spl times/62 /spl mu/m/SUP 2/ was obtained.
Keywords
Field effect integrated circuits; Integrated circuit technology; Integrated memory circuits; Large scale integration; Random-access storage; field effect integrated circuits; integrated circuit technology; integrated memory circuits; large scale integration; random-access storage; Biographies; Circuits; Electric variables; Fabrication; Laboratories; Large scale integration; Read-write memory; Silicon; Substrates; Transistors;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1978.1051112
Filename
1051112
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