Title :
Advanced `contact engineering´ for submicron VLSI multilevel metallization
Author :
Young, K. Konrad ; Riley, Paul E. ; Uesato, W. ; Whetten, T.J. ; Hu, H.K. ; Ray, G.W. ; Peng, Shiesen ; Chiu, Kuang-Yi
Author_Institution :
Hewlett Packard Co., Palo Alto, CA, USA
fDate :
2/1/1993 12:00:00 AM
Abstract :
Two contact engineering methods developed for submicron contact openings are described. The two methods, SCOPE (simultaneous contact and planarization etch) and PACE (planarization after contact etch), interchange the process sequences of dielectric planarization and contact etch to achieve uniform contact etch. Both etching processes eliminate the need for oxide reflow thereby minimizing the thermal budget after source/drain formation. Since the dielectric is planarized either during the contact etch (e.g., with SCOPE) or after contact etch (e.g., with PACE), the need for extensive overetching of the oxide due to the dissimilar contact depths is also eliminated. As a result, contact resistance and leakage currents are significantly reduced in comparison to results obtained with dielectrics planarized before etching. In addition, etching of field oxide due to pattern misalignment is minimized since the contacts are of similar depth
Keywords :
CMOS integrated circuits; VLSI; contact resistance; leakage currents; metallisation; CMOS; PACE; SCOPE; VLSI; contact etch; contact resistance; dielectric planarization; etching processes; leakage currents; multilevel metallization; planarization after contact etch; process sequences; simultaneous contact and planarization etch; submicron contact openings; Contact resistance; Dielectrics; Etching; Leakage current; Metallization; Planarization; Resists; Silicides; Silicon; Very large scale integration;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on