CMOS/SOS memory circuits for radiation environments

Memory circuit techniques which combine radiation hardness with high density, high speed, and low power dissipation have been developed. CMOS/SOS circuits featuring self-compensation, self-biasing, and parameter tracking accommodate a wide range of nonuniform on-chip parameter variations. These variations may occur as the result of exposure to a nuclear radiation event or from MOS device processing, temperature, or power-supply effects. The circuits discussed in this paper are key elements for radiation-hardened memory designs [up to 10/SUP 6/ rad (Si)] with state-of-the-art LSI density and performance. The CMOS/SOS memory cell sizes (3.1 mil/SUP 2/ for a six-device static cell and 2.5 mil/SUP 2/ for a four-device static cell) are nearly five times smaller than previous radiation-hardened cells.