• DocumentCode
    886182
  • Title

    Radiation-Tolerant 50MHz Bulk CMOS VLSI Circuits Utilizing Radiation-Hard Structure Nmos Transistors

  • Author

    Hatano, Hiroshi ; Takatsuka, Satoru

  • Volume
    33
  • Issue
    5
  • fYear
    1986
  • Firstpage
    1126
  • Lastpage
    1130
  • Abstract
    A radiation-tolerant, high-speed, bulk CMOS VLSI circuit design, utilizing a new NMOS structure, has been investigated, based on ¿-ray irradiation experimental results for 2¿m shift registers. By utilizing 60-bit clocked gate and transfer gate static shift register circuits, the usefulness of radiation-hard NMOS structure and circuit design parameter optimization has been confirmed experimentally, showing 50 MHz operation CMOS circuits at 5 V supply voltage after 1 × 105 rads (Si) irradiation. The limitations of dynamic circuits in radiation-tolerant circuit designs have also been shown, using 120-bit dynamic shift register circuits. Based on the above results, radiation-tolerant, high-performance, bulk CMOS VLSI circuit designs are discussed.
  • Keywords
    Circuit synthesis; Clocks; Degradation; Design optimization; Inverters; MOS devices; MOSFETs; Shift registers; Threshold voltage; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.1986.4334551
  • Filename
    4334551