Low-power CMOS digital design

Author

Chandrakasan, Anantha P. ; Sheng, Samuel ; Brodersen, Robert W.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

27

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

473

Lastpage

484

Abstract

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; integrated logic circuits; CMOS digital design; Si area; battery-operated applications; computational throughput; design tradeoff; digital ICs; intensive computation; logic style; low-power operation; optimum voltage; portable environments; power consumption; scaling strategy; technology optimizations; CMOS digital integrated circuits; CMOS logic circuits; CMOS technology; Coupling circuits; Digital circuits; Energy consumption; Logic circuits; Portable computers; Throughput; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.126534

Filename

126534