• DocumentCode
    886308
  • Title

    Solving the gate packing problem using a concurrent network

  • Author

    Lin, Fujian ; Lee, Kuan-Chou

  • Author_Institution
    Santa Clara Univ., CA, USA
  • Volume
    28
  • Issue
    20
  • fYear
    1992
  • Firstpage
    1876
  • Lastpage
    1878
  • Abstract
    The layout problem of gate matrices and one-dimensional logic arrays is composed of two major tasks: to find a permutation of gates which minimises the number of tracks required and to layout/pack gates based on the ordering. A parallel algorithm is presented which can pack n gates within O(1) time, whereas the conventional near-optimum algorithm needs O(n2) time. The simulation results show that the increase of the problem size does not degrade the solution quality.
  • Keywords
    circuit layout CAD; logic CAD; logic arrays; neural nets; parallel algorithms; concurrent network; digital design; gate matrices; gate packing problem; gate permutation; layout problem; one-dimensional logic arrays; parallel algorithm; simulation; track number minimisation;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19921201
  • Filename
    161227
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=886308