Highly parallel collision detection processor for intelligent robots

Author

Kameyama, Michitaka ; Amada, Tadao ; Higuchi, Tatsuo

Author_Institution

Tohoku Univ., Sendai, Japan

Volume

27

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

500

Lastpage

506

Abstract

A collision detection VLSI processor is proposed in order to achieve ultrahigh-performance processing with an ideal parallel processing scheme. A large number of coordinate transformations and memory accesses to the obstacle memory are fully utilized in the processing algorithm, so that direct collision detection can be executed with a VLSI-oriented regular data flow. The structure of each processing element (PE) is very simple because a PE mainly consists of a COordinate Rotational DIgital Computer (CORDIC) arithmetic unit for the coordinate transformation and memories for the storage of manipulator and obstacle information. When 100 PEs are used for parallel processing, the performance is about 10,000 times faster than that of conventional approaches using a single general-purpose microprocessor

Keywords

CMOS integrated circuits; VLSI; industrial robots; microprocessor chips; parallel architectures; planning (artificial intelligence); position control; CORDIC arithmetic unit; VLSI processor; VLSI-oriented regular data flow; collision avoidance; coordinate transformation; coordinate transformations; direct collision detection; ideal parallel processing scheme; intelligent robots; memory accesses; motion planning; obstacle memory; parallel collision detection processor; parallel processing; performance; processing algorithm; Engine cylinders; Intelligent robots; Manipulators; Motion detection; Motion planning; Orbital robotics; Parallel processing; Process planning; Robot kinematics; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.126537

Filename

126537