Fault-tolerant architecture in a cache memory control LSI

Author

Ooi, Yasushi ; Kashimura, Masahiko ; Takeuchi, Hidenori ; Kawamura, Eiji

Author_Institution

NEC Corp., Kanagawa, Japan

Volume

27

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

507

Lastpage

514

Abstract

A real-time degradable four-way set-associative cache memory control (CMC) LSI is described. Three kinds of errors, address parity error, comparator error, and multihit error, can cause functional degradation by killing the associative unit corresponding to the fault detection. The parity generator and the double comparator have no effect on the timing-sensitive path delay because of the parallel configuration of the circuits. The multihit detector occupies about 16% of the propagation delay of the critical path, from the external address input to the hit/miss output

Keywords

CMOS integrated circuits; VLSI; buffer storage; fault tolerant computing; storage management chips; address parity error; cache memory control LSI; comparator error; double comparator; fault detection; fault tolerant architecture; functional degradation; hit/miss output; multihit detector; multihit error; parallel configuration; parity generator; set-associative cache memory control; timing-sensitive path delay; Cache memory; Circuits; Degradation; Delay effects; Detectors; Electrical fault detection; Error correction; Fault detection; Fault tolerance; Large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.126538

Filename

126538