• DocumentCode
    886402
  • Title

    Unidirectional systolic multiplier

  • Author

    Ait-Boudaoud, D.

  • Author_Institution
    Bournmouth Univ., Poole, UK
  • Volume
    28
  • Issue
    20
  • fYear
    1992
  • Firstpage
    1893
  • Lastpage
    1894
  • Abstract
    A high throughput unidirectional systolic multiplier is presented. The new architecture is based on the cell merging approach, where each basic building unit is a radix-2 bit-level cell. A comparison with the existing pipelined multiplier shows that the proposed architecture reduces the latency by at least 40%.
  • Keywords
    digital arithmetic; multiplying circuits; systolic arrays; architecture; cell merging; high throughput; latency-reduction; parallel architecture; radix-2 bit-level cell; unidirectional systolic multiplier;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19921211
  • Filename
    161237
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=886402