Title :
A high-speed sensing scheme for 1T dynamic RAMs utilizing the clamped bit-line sense amplifier
Author :
Blalock, Travis N. ; Jaeger, Richard C.
Author_Institution :
Dept. of Electr. Eng., Auburn Univ., AL, USA
fDate :
4/1/1992 12:00:00 AM
Abstract :
A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to the initial bit-line difference voltage. The CBLSA maintains a low impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power
Keywords :
CMOS integrated circuits; DRAM chips; CMOS IC; DRAM; clamped bit-line sense amplifier; dynamic RAM; high-speed operation; high-speed sensing scheme; one-transistor cell; Capacitance; Circuit noise; Circuit testing; Coupling circuits; DRAM chips; Impedance; Operational amplifiers; Power supplies; Random access memory; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
