Short-channel MOSFETs in the punchthrough current mode

Author

Barnes, John J. ; Shimohigashi, Katsuhiro ; Dutton, Robert W.

Volume

14

Issue

2

fYear

1979

fDate

4/1/1979 12:00:00 AM

Firstpage

368

Lastpage

375

Abstract

Results of two-dimensional device analysis are compared with experiment for 0.8-μm Si-gate ion-implanted MOS devices operated under conditions of punchthrough transport. Characterization of the punchthrough mode of device operation with experiment and simulation has shown that the observed power-law dependence is related to the drain-induced barrier-height lowering. Results of the simulation show the dependence of the punchthrough current upon the range and maximum doping level of the channel implantation. Increasing the substrate-bias or applying a negative-gate voltage is shown to increase the punchthrough voltage. This simulation, which combines results of the process-simulation program and device-simulation program, is shown to predict the behavior of this mode of operation where previous one-dimensional theory has failed.

Keywords

Insulated gate field effect transistors; Large scale integration; Semiconductor device models; insulated gate field effect transistors; large scale integration; semiconductor device models; Breakdown voltage; Circuit simulation; Doping profiles; Intrusion detection; Ion implantation; Laboratories; MOS devices; MOSFETs; Semiconductor process modeling; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1979.1051187

Filename

1051187