Total Dose Radiation-Hardened Latch-Up Free CMOS Structures for Radiation-Tolerant VLSI Designs

In order to design radiation-tolerant CMOS VLSI circuits, six different radiation-hardened structures including SOS, have been investigated utilizing 4-bit clocked CMOS static shift registers with a 5 V supply voltage. Packing density has been compared, utilizing clocked CMOS static shift register cells which have been designed using the same 2 ¿m design rules. Total dose radiation test results and latch-up holding voltages have been shown. Propagation delay times have also been shown, utilizing nineteen-stage CMOS ring oscillators. Based on the above results, the usefulness of thin field oxide introduced between source/drain diffusion layers and thick field oxide, combined with epitaxial or SOS substrate is discussed for use in radiation-tolerant CMOS VLSI designs.