A pulsed sensing scheme with a limited bit-line swing

Author

Scheuerlein, R.E. ; Katayama, Y. ; Kirihata, T. ; Sakaue, Y. ; Satoh, A. ; Sunaga, T. ; Yoshikawa, T. ; Kitamura, K. ; Dhong, S.H.

Author_Institution

IBM Japan, Tokyo, Japan

Volume

27

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

678

Lastpage

682

Abstract

A pulsed sensing scheme with a limited bit-line swing designed for 4-Mb CMOS high-speed DRAMs (HSDRAMs) and beyond is presented. It uses a standard CMOS cross-coupled sense amplifier and limits the swing by means of a pulsed sense clock. The signal loss that would occur if the bit-line swing were not exactly limited to one threshold above the word-line´s low level is avoided by using a small reference voltage generator and trench decoupling capacitors. The sensing scheme was successfully implemented on an experimental HSDRAM fabricated by using 0.7-μm L_eff CMOS technology, and a high-speed random access time of 15 ns and a low power dissipation of 144 mW were obtained for 512-kb array activation with a fast cycle time of 60 ns at 3.6 V

Keywords

CMOS integrated circuits; DRAM chips; 0.7 micron; 144 mW; 15 ns; 3.6 V; 4 Mbit; 512 kbit; 60 ns; CMOS; cross-coupled sense amplifier; cycle time; dynamic RAM; high-speed DRAMs; limited bit-line swing; power dissipation; pulsed sense clock; pulsed sensing scheme; random access time; reference voltage generator; trench decoupling capacitors; CMOS technology; Capacitors; Clocks; Energy consumption; Hardware; Laboratories; MOS devices; Pulse amplifiers; Pulse circuits; Stability;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.126563

Filename

126563