Consideration of poly-Si loaded cell capacity limits for low-power and high-speed SRAMs

Author

Kato, H. ; Sato, K. ; Matsui, M. ; Shibata, H. ; Hashimoto, K. ; Ootani, T. ; Ochii, K.

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

27

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

683

Lastpage

685

Abstract

The maximum bit capacity of poly-Si loaded SRAMs is estimated, based on cell stability limits. When SRAM density increases, the voltage level of a storage node in the high state decreases more quickly because of MOS drain leakage current that flows in the poly-Si load; this can prevent regular cell operation. The poly-Si load resistance and the drain leakage current distribution are measured by using special 0.8-μm 1-Mb SRAM test chips. The maximum bit capacity is then calculated for low-power and high-speed SRAMs. The limit is 4 Mb for low-power SRAMs and 4 Gb for high-speed SRAMs

Keywords

CMOS integrated circuits; SRAM chips; current distribution; elemental semiconductors; leakage currents; silicon; 0.8 micron; 1 Mbit; 4 Gbit; 4 Mbit; CMOS memory chip; MOS drain leakage current; capacity limits; cell stability limits; current distribution; high-speed; low-power; maximum bit capacity; poly-Si loaded cell; polycrystalline Si; polysilicon; static RAM; Current measurement; Electrical resistance measurement; Equivalent circuits; Leakage current; MOSFETs; P-n junctions; Random access memory; Semiconductor device measurement; Stability; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.126564

Filename

126564