DocumentCode
886920
Title
A Computer-Oriented Factoring Algorithm for NOR Logic Design
Author
Dietmeyer, D.L. ; Schneider, P.R.
Author_Institution
Department of Electrical Engineering, University of Wisconsin, Madison, Wis.
Issue
6
fYear
1965
Firstpage
868
Lastpage
874
Abstract
Because transistor NOR gates allow only a liitmed number of inputs, NOR equations must be factored before they can be implemented. An easily programmed algorithm is developed which rapidly generates a subset of factors, selects optimum factors, and indicates a realization for the factored equation based on the relation A ¿ B ¿ C ¿ D = [(A ¿ B) ¿] ¿ C ¿ D. A method for preventing excessive fan-out is also presented.
Keywords
Algorithm design and analysis; Circuit synthesis; Cost function; Equations; Hardware; Logic circuits; Logic design; Packaging; Power generation; Tellurium;
fLanguage
English
Journal_Title
Electronic Computers, IEEE Transactions on
Publisher
ieee
ISSN
0367-7508
Type
jour
DOI
10.1109/PGEC.1965.264081
Filename
4038606
Link To Document