Single Event Effects in High Density CMOS SRAMs

The effects of epi-substrate and a cell power supply layout on heavy-ion induced latch-up for 64K SRAMs are examined by heavy-ion exposure tests using a cyclotron. It is shown that epi-substrate alone is not sufficient to prevent latch-up. A cell power supply layout technique, that is, power is supplied through the well for MOSFETs in the well, combined with epi-substrate is very effective in preventing latch-up for high density CMOS/BULK memories. Soft error cross sections and threshold LETs for various CMOS SRAMs are determined by heavy-ion exposure tests. The threshold LET for conventional 64K SRAMs decreases to about one-fifth that of 1K SRAMs.